Design files correspond to vhdl and verilog files. Design files can be edited outside of the project scope with a limited set of functionallity, but are required to be underneath the design directory.

Creating a Design File

Design files can be created either by just creating a new file with a .vhd or .vhdl extension or by using one of the new file wizards.

1. Right click on a folder in the navigator view beneath the design directory and select New->{Vhdl Entity or Vhdl Package}
2. Enter a name with a vhdl or vhd extension in the dialog